1. Field of the Invention
This invention relates in general to an integrated circuit and more specifically to well biasing circuitry for transistors of an integrated circuit.
2. Description of the Related Art
Integrated circuits utilize transistors, such as e.g. CMOS transistors, for implementing logic circuitry of the integrated circuit. In one example, logic circuitry is implemented in rows of cells of an integrated circuit. These rows may contain N well areas and P well areas that are utilized to implement the transistors of the logic circuitry.
In some embodiments, during the normal operation of the integrated circuit, the N well area is biased with a supply voltage of VDD and the P well area is biased with a supply ground voltage VSS. For some transistor types, such as CMOS, the sub threshold leakage current of the transistors may be unacceptably large, such that the integrated circuit draws large amounts of current during standby. In order to reduce power during standby, the N well areas maybe biased with a voltage that is higher than the supply voltage VDD and the P well areas may be biased with a voltage that is lower than the supply voltage VSS. However, circuitry for selectively biasing the well areas of an integrated circuit may occupy an unacceptable amount of space of the integrated circuit and/or may generate a large amount of inrush current during a change in well bias voltages.
What is needed is improved circuitry for selectively biasing the well areas of an integrated circuit.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.